1. Field
This disclosure relates generally to computer processor architecture, and more specifically, to configuring a computer processor for latency tolerance execution.
2. Related Art
One goal of ongoing processor development is to increase the number of instructions per cycle (IPC). A computer processor's IPC is typically limited by stalling of instructions in queues due to the inability to access memory when instructions are executed in-order. Issuing instructions out-of-order can help to a certain degree, but eventually stalled instructions will block other independent instructions from execution as out-of-order dependent instructions fill up the queue.
Further, there is ever-increasing pressure to reduce power consumption in computer processor devices to conserve available power and extend the operating life of portable devices between re-charging cycles.